1. Field of the Invention
The present invention relates to semiconductor devices and a method of manufacturing the same, and more particularly, to a semiconductor device having an MOS transistor and a method of manufacturing the same.
2. Description of the Background Art
As an N channel type MOS transistor mounted on a semiconductor device, such a structure as shown in FIG. 67 is conventionally known. Referring to FIG. 67, in this conventional semiconductor device, on the main surface of a semiconductor substrate 1 formed of a P type silicon substrate, formed is an element isolation oxide film 2 so as to surround an N channel type MOS transistor forming region. Element isolation oxide film 2 is for electrically insulating the N channel type MOS transistor forming region from an element formed adjacent thereto. A channel stopper region 3 formed of a P.sup.+ type impurity region is provided under element isolation oxide film 2. A pair of source/drain regions 4 and 5 are formed on the main surface of the N channel type MOS transistor forming region so as to sandwich a channel region 6. A gate electrode 8 is formed on channel region 6 with a gate insulating film 7 interposed therebetween. The pair of source/drain regions 4 and 5 and gate electrode 8 configure an N channel type MOS transistor.
Such a conventional N channel type MOS transistor as structured above has suffered from the following problems as miniaturization progresses. More specifically, when the N channel type MOS transistor is rendered non-conductive, hot carriers are generated by the high electric field occurring at an end portion of one source/drain region (hereinafter uniquely defined as drain region 4, with the other source/drain region uniquely defined as source region 5) functioning as a drain of the pair of source/drain regions 4 and 5 in contact with channel region 6. The generated hot carriers are implanted into gate insulating film 7. The hot carriers implanted and caught in gate insulating film 7 cause degradation in accordance with time of transistor characteristics such as change in the threshold voltage of the transistor, reduction of drain current, or the like, that is, so-called hot carrier degradation. Now, detailed description of the hot carrier degradation will be given. The hot carrier degradation is a phenomenon that a channel hot electron (CHE) implantation or drain avalanche hot carrier (DAHC) implantation causes degradation of transistor characteristics such as change in the threshold voltage and reduction of drain current. The channel hot electron implantation is a phenomenon that electrons in channel region 6 get hot with energy from the electric field in the direction along the channel, and that hot electrons which are finally supplied with energy larger than the height of an energy barrier of the interface between the semiconductor substrate and gate insulating film 7 are implanted into gate insulating film 7 over the energy barrier. This phenomenon is called channel hot electron implantation.
The drain avalanche hot carrier implantation is a phenomenon that electrons in channel region 6 supplied with high energy due to the large electric field in the vicinity of drain region 4 generate electron-hole pairs by ionization impact with photons or an avalanche phenomenon. These electrons or holes, or both get hot and are implanted into gate insulating film 7. This phenomenon is called drain avalanche hot carrier implantation.
Such channel hot electron implantation or drain avalanche hot carrier implantation causes electrons or holes to be caught in the interface between semiconductor substrate 1 in the vicinity of drain region 4 and gate insulating film 7, and to be trapped in the interface state in gate insulating film 7 in the vicinity of the interface. The channel hot electron implantation or drain avalanche hot carrier implantation causes electrons or holes to generate the interface state. As a result of electrons and holes being trapped in the interface state, or generation of the interface state, degradation of transistor characteristics such as change in the threshold voltage and reduction of drain current is observed. This phenomenon is called hot carrier degradation.
As one method of alleviating such problems as described above, an MOS transistor having a so-called LDD (Lightly Doped Drain) structure shown in FIG. 68 is known. Referring to FIG. 68, in the MOS transistor having the LDD structure, the source/drain regions are configured of low impurity concentration diffusion regions 4a and 5a in contact with channel region 6 at their end portions, and high impurity concentration diffusion regions 4b and 5b positioned outside of channel region 6 and integrally formed with low impurity concentration diffusion regions 4a and 5a. A sidewall oxide film 9 is further formed so as to be in contact with the side surface of gate electrode 8, the side surface of gate insulating film 7 and the main surface of semiconductor substrate 1. The pair of source/drain regions 4 and 5, gate electrode 8, and sidewall oxide film 9 configure the N channel type MOS transistor.
Such an N channel type MOS transistor structured as described above is manufactured as follows. First, gate insulating film 7 and gate electrode 8 are formed on the main surface of semiconductor substrate 1. With gate electrode 8 used as part of a mask, N type impurities are implanted into the main surface of semiconductor substrate 1 to form a pair of low impurity concentration diffusion regions 4a and 5a.
Then, an oxide film (not shown) is formed on the main surface of gate electrode 8 and the pair of low impurity concentration diffusion regions 4a and 5a with a CVD method. After that, the oxide film is anisotropically etched. As a result, sidewall oxide film 9 is formed in contact with the side surface of gate electrode 8, the side surface of gate insulating film 7, and the pair of low impurity concentration diffusion regions 4a and 5a. With gate electrode 8 and sidewall oxide film 9 used as part of a mask, N type impurities are implanted into the main surface of semiconductor substrate 1 to form high impurity concentration diffusion regions 4b and 5b. As described above, sidewall oxide film 9 functions as a mask for forming high impurity concentration diffusion regions 4b and 5b of the pair of source/drain regions 4 and 5 in a self-alignment manner.
Since the end portion of drain region 4 in contact with channel region 6 is low impurity concentration diffusion region 4a in such an N channel type MOS transistor structured as described above, the electric field of the end portion of drain region 4a is alleviated. As a result, implantation of hot carriers into gate insulating film 7 is advantageously suppressed, so that the reliability is increased.
As miniaturization further progresses, however, hot carriers are implanted into sidewall oxide film 9 provided in order to form the LDD structure. The hot carriers caught in sidewall oxide film 9 inconveniently cause the interface state to be generated at the interface between sidewall oxide film 9 and semiconductor substrate 1. This results in reduction of the mobility, which in turn decreases drain current.